This invention relates to barrier synchronization processing in a parallel computer and, more specifically, a computer capable of multiple barrier synchronization operations.
Barrier synchronization is common in parallel computers in which plural processors are each assigned a thread (or process) to compute separately. Through barrier synchronization processing, the processors are synchronized with one another at a barrier synchronization point set to each thread in advance.
For example, in a Symmetric Multiprocessing (SMP) parallel computer, plural symmetric multiple processors share a memory, which enables a thread on each processor to access data stored in the shared memory by other threads and to exchange computation results with other threads. Synchronization processing to confirm that each thread has finished computation up to a preset synchronization point allows the threads to synchronize with one another each time computation processing set in advance is completed and to start next computation simultaneously. The processors are synchronized by keeping each processor from starting on computation beyond its synchronization point until all of the processors reach their synchronization points set by a program in advance. One of known techniques for performing such processor synchronizing processing at high speed is a barrier synchronization mechanism by hardware (see JP 11-312148 A, for example).
A recent trend is to employ a multicore microprocessor in which plural processor cores are mounted to one LSI package, and to improve the processing speed of parallel processing by preparing plural physical processor cores. Further, applications and OSs contribute to smooth and swift parallel processing by dividing one task into plural threads (or processes).